Research on Integrated Circuit Copper Interconnection and Related Issues

2 = SimSun process and related process questions, discussed the role of barrier materials and selection principles, and also made a brief progress on the research of low materials. I Introduction With the development of ultra-large integrated circuits, 151, the packaging density continues to increase The circuit elements are getting denser and denser, which leads to a continuous decrease in the cross-sectional area and line spacing of 181 metal interconnects. The increased interconnect resistance and parasitic capacitance greatly increase the time constant of the interconnect. At this time, the speed of 1 will be changed from the logic gate delay time control to the time constant hole of the interconnection line, which plays the main control role. 1. If the current connection is still used and the only way is to increase the interception of the interconnection line Area and line spacing. However, this will reduce the length of the wiring within the unit area of ​​each layer of wiring. If the package density is maintained, the number of interconnect lines must be increased. According to calculations, the number of layers of 0.13 Wah process 1 wiring will exceed 10 layers, and the increase in the number of interconnection process steps will lead to a decrease in yield. In fact, it is difficult to realize interconnection wiring of more than 10 layers even with a wider feature size process of 35 melons. Obviously, in order to fundamentally solve the above problems, it is necessary to use a metal with lower resistivity as the interconnect material. At the same time, as the thickness of the interlayer dielectric continues to decrease, the dielectric constant of the interlayer dielectric must also be reduced to maintain the same capacitance, so the development of low-value dielectric materials is also required 12.

When the female material is used as an interconnect system, the number of interconnect layers required for different feature sizes 3.

In this context of demand. In recent years, CU has replaced the traditional A1 as a new interconnect metal and has become a research hotspot in the solid electronics field. It will break the characteristics and face of the interconnect material since June 1 has been used as an interconnect material. Q briefly discusses the role and selection principles of barrier materials, and also introduces the implementation of 1 interconnection process and the research of low-skin materials. The size and characteristics of 2 different interconnection systems are important for the number and characteristics of metal slaughter. The relationship between the size 2, the characteristics of the interconnection line and the problems faced as a ram, lu, hydrazine material, squat, squat, squirrel, nogaki, autumn, the resistivity is 35. lower than that of aluminum. Resistance, but also improve some other properties. For example, the power consumption of an interconnection line is low, and the anti-electromigration performance is two orders of magnitude higher than 41, so that it is estimated that it will be replaced by, after.

The resistance of the interconnect line is reduced by 40. If the low-value dielectric material is used instead of 3, the parasitic capacitance can be reduced by 50. The low-moxibustion value dielectric material system can increase the speed of 1 by 4 times = so people think that it will become the next generation of 1 The wiring material, however, 0, as the interconnection material, there are also the following aspects: 1 in 5; and the oxide diffuses quite fast, and once it enters the Fen device, it will become a deep-level acceptor impurity and degrade the performance of the device Even failure 2 is a stable metal. In dry corrosion, it cannot produce volatile halides. Min can't use the conventional plasma etching process to prepare interconnected lines. 3 It is easy to change under air and low temperature in 2000, and it can't form a protective layer to prevent its own progress from being oxidized and corroded. 6 This requires the development of a completely different process from 6 to 1. Overcoming the above-mentioned problems, the solutions of the problems constitute the focus of the current research on the interconnection process, and the main research focuses on the preparation of the material of the crotch barrier layer that prevents diffusion and the shape of the 0 interconnection.

31 interconnection line preparation process due to, 1 is used for some questions when interconnecting lines. In order to prevent and diffuse the design of the lead structure, it must be completely encapsulated by the barrier material, and it is difficult to form with the existing plasma corrosion in the process of realization. The interconnection shape of 1 is 0. Known as the damascene process, the 3 interconnection line preparation technology is first used in the interconnection process 13 is 81 prepared with 6 layers, チ, wipe 103 circuit This technology is first through photolithography and reaction according to the interconnection shape Ion etching forms trenches on the medium that needs to interconnect the chips. Deposited in the trench, the barrier layer Ta or TaN1 and then add the CU deposit into the trench tip, followed by metal chemical mechanical polishing, remove the formation of the line shape and complete the planarization of the layer, and finally on the 1 The mosaic process of the passivation layer of the deposition layer Magic 3 is divided into the double soil embedding process and the single mosaic process. The so-called dual damascene process simultaneously prepares the through-hole and the process wiring of this layer, and they are prepared separately in the single damascene process. Because the dual damascene process is less than the single, damascene process and the current connection process based on material removal is reduced by 30 Process, so the double-bonded embedding process is widely used in the preparation of interconnection. The process of this god process is shown in 036 exhibitions, 1 interconnection line, 5 circuits. A thin silicon nitride film, which acts as a corrosion barrier when corroding wiring trenches, and also blocks zero diffusion. As is known to all, in the preparation of the interconnection line 1, the etching of the etched metal or dielectric layer stops on the barrier material layer, and the etching is made uniform by appropriate over-etching. In the dual damascene process, if the corrosion barrier layer is not added between the through hole and the wiring dielectric layer, the corrosion depth is difficult to control, because the corrosion depth is required to reach an appropriate intermediate position. With the silicon nitride corrosion barrier, a uniform depth of corrosion can be obtained. But silicon nitride has a high dielectric constant, so the silicon nitride layer should be made as thin as possible to avoid increasing the interlayer capacitance.

Since the connection formed by the dual damascene process is achieved by digging trenches in the dielectric layer with true charge, unlike the 1 connection, it is formed by etching the metal, thus avoiding the difficulty of the 1 connection process. It is necessary to choose a deposition method suitable for the damascene process. The currently used deposition methods are physical vapor deposition printing, chemical vapor deposition electrochemical deposition 00, ionization, 00 and electroplating. Among them, electroplating is a commonly used method 8, 9 which has excellent gap filling capabilities, high deposition rate, low deposition temperature, simple system and easy control of the deposition process. However, electroplating requires a seed layer and requires a continuously conductive substrate. At present, the seed layer is prepared by, or.

4 Barrier layer and seed layer In the preparation process of 1 interconnection line, metal corrosion is a key process because it determines the line width and spacing of the interconnection line. The damascene process of the interconnection line avoids the corrosion of the interconnection line shape, and uses a simpler line width and spacing. However, the damascene process requires the deposition of the barrier layer seed layer and Cu material in the wiring trench with a relatively large height and width.

The barrier layer plays a dual role of preventing the thermal diffusion of the interconnection line 01 into the active area of ​​the device and improving the adhesion of 01 to the dielectric material. These two factors should be considered when selecting the barrier layer material. For example, if the barrier layer does not react at all, it will have excellent blocking effect on atomic diffusion, but it will have poor adhesion; if it is easy to react with, although it does, it has good adhesion Attached, but not as a barrier. Therefore, considering good barrier properties and adhesion, the ideal barrier layer material reacts with the CU to have a self-limiting range. The currently studied barrier materials include Ding Ping, 1 team Ding, Ding Huading 38, etc. 10.

Ding and 1 are considered to be excellent barrier materials.

A detailed study of the TaCu interface revealed that after annealing at 400C for approximately one hour, an amorphous layer of about 3! 1 will be formed at the interface. The formation of the amorphous layer improves the adhesion between the two. Progressive experiments show that the thickness of the amorphous layer does not increase with the increase of annealing temperature, and is saturated at about 4 out. Ding 50073, 1 interface is still quite stable.

e trenches and vias are etched to deposit barrier layers and seed layers; f copper deposition; g copper CMP and top SiN deposition 5 ⑶ low-level dielectric materials in the wiring system, the mouth reduces the resistance of the interconnection, but if To greatly reduce the time constant of the interconnection line, it is necessary to fill the low-moxibustion dielectric 3 between the interconnection layer and the line, and the value of moxibustion 4, 8102 is about 4, to reduce the capacitance of the interconnection line. Therefore, in connection with the CU, the research of low moxibustion materials has attracted great attention, and a variety of low value materials have been developed. 1 gives the values ​​of these materials and the preparation process. 13. From the preparation process, the low Value materials can be prepared by spin coating dielectric 500 method or chemical vapor deposition, 0 method. The material investment of 800 material is small, its nature is not determined by the deposition process, but by the baking and heat treatment process after deposition. Most materials with a low moxibustion value of 800 require a liner layer to improve the bond with the substrate, and a cover layer on top to resist moisture, which is also conducive to the use of 01. , 6861 is a two-phase system with a porosity of 75 and a dielectric constant of 1.8, made by Ding 1 company. The resistance and capacitance of the 1 interconnection system are reduced by 30 and 14.

Moxibustion value preparation process Among the 1-moxibustion value materials made of poly-p-benzyl xerogel, along 0 is a competitive type with high chemical and mechanical stability, which can be obtained with standard 0.

6 Concluding remarks, this process has been applied to microprocessor high-performance memory and digital signal processors. For example, at the end of 1998, it was announced that they used Cu interconnects to produce the 400MHz microprocessor PowerPC740750 series and embedded Power. They are also used in 3390, 86000 and 8400 series microprocessors, interconnect technology. Announced on March 1, 1999, 1 interconnection technology produced the world's fastest 18. Price 8 etc. all announced that there will be more 1 products using 0 interconnection lines. Obviously, the interconnect technology will play an increasingly important role in production.

Song Dengyuan male, associate professor, director of the teaching and research section. Graduated from the Department of Electronic and Information Engineering of Hebei University in 1982. He used to be a visiting scholar to study at GRFFFTH University in Australia. Has been issued at home and abroad